LIBRARY IEEE;
USE IEEE.Std_logic_1164.ALL;
ENTITY rotator IS
PORT(clk:IN Std_logic; led:OUT Std_logic_vector(7 DOWNTO 0));END rotator;
ARCHITECTURE behavl OF rotator IS
SIGNAL state:Std_logic_vector(3 DOWNTO 0); SIGNAL dir:std_logic;BEGIN
PROCESS(clk) BEGINIF clk'Event AND clk = '1' THEN
CASE state IS
WHEN "0000" => state <= "1000"; dir <= '0'; WHEN "1000" => IF dir = '0' THEN state <= "1100"; ELSE state <= "0000"; END IF; WHEN "1100" => IF dir = '0' THEN state <= "1110"; ELSE state <= "1000"; END IF; WHEN "1110" => IF dir = '0' THEN state <= "1111"; ELSE state <= "1100"; END IF; WHEN "1111" => state <= "1110"; dir <= '1'; WHEN OTHERS=> state <= "0000";END CASE;
END IF;
END PROCESS; led(7) <= state(3); led(0) <= state(3); led(6) <= state(2); led(1) <= state(2); led(5) <= state(1); led(2) <= state(1); led(4) <= state(0); led(3) <= state(0);END behavl;
用VHDL语言设计一个七段显示译码器电路，要求输出信号为高电平有效, 能驱动共阴极数码管。
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity shukong is
port{
clk250:in std_logic;
d:in std_logic_vector(3 downto 0);
divclk:out std_logic
};
end entity;
architecture be of shukong is
variable full:std_logic;
variable clk1:std_logic_vector(3 downto 0);
begin
process(clk250)
begin
if clk250'event and clk = '1' then
if clk1 = "1111" then
clk1 <= d;
else clk1 := clk1 + 1;
end if;
end if;
end process;
process(clk1)
if clk1 = 1 then full := 0;
else full := 1;
end if;
end process;
divclk <= full;
end architecture;
这是个数控分频，11分频只要d赋值为“1011”就可以了
下面是74LS49的VHDL描述，74LS49就是一个驱动共阴极数码管的译码器：
LIBRARY IEEE；
USE IEEE.Std_logic_1164.ALL；
ENTITY ls49 IS
PORT(bl_n：IN Std_logic；
bi：IN Std_logic_vector(3 DOWNTO 0)；
a，b，c，d，e，f，g：OUT Std_logic)；
END ls49；
ARCHITECTURE behave_49 OF ls49 IS
SIGNAL s:Std_logic_vector(6 DOWNTO 0)；
BEGIN
PROCESS（bi，bl_n）
BEGIN
IF bl_n = ′0′ THEN
s <= (OTHERS => ′0′)；
ELSE
CASE bi IS
WHEN ″0000″ => s <= B″011_1111″；
WHEN ″0001″ => s <= B″000_0110″；
WHEN ″0010″ => s <= B″101_1011″；
WHEN ″0011″ => s <= B″100_1111″；
WHEN ″0100″ => s <= B″110_0110″；
WHEN ″0101″ => s <= B″110_1101″；
WHEN ″0110″ => s <= B″111_1101″；
WHEN ″0111″ => s <= B″010_0111″；
WHEN ″1000″ => s <= B″111_1111″；
WHEN ″1001″ => s <= B″110_1111″；
WHEN ″1010″ => s <= B″101_1000″；
WHEN ″1011″ => s <= B″100_1100″；
WHEN ″1100″ => s <= B″110_0010″；
WHEN ″1101″ => s <= B″111_1001″；
WHEN ″1110″ => s <= B″111_1000″；
WHEN ″1111″ => s <= B″000_0000″； -- 熄灭
WHENOTHERS=> s <= (OTHERS => ′0′)； -- 熄灭
END CASE；
END IF；
END PROCESS；
a <= s(0)；
b <= s(1)；
c <= s(2)；
d <= s(3)；
e <= s(4)；
f <= s(5)；
g <= s(6)；
END behave_49；
