`timescale 1ns / 1ps
`define IDLE 4'b0000
`define S1 4'b0001
`define S2 4'b0010
`define S3 4'b0100
`define S4 4'b1000
module LED(clk,SW,BTN_EAST,LED
);
parameter delay=32'hFBC520; // 33MHz, set 0.5s here
input clk,SW,BTN_EAST;
output [7:0] LED;
wire rst_int;
wire run;
reg [31:0] counter;
reg [3:0] tmp;
reg [3:0] state;
reg [7:0] ledreg;
//run
assign run=SW;
//reset
assign rst_int=!BTN_EAST;
//count for 0.5s;
always@(posedge clk or negedge rst_int)
if(!rst_int)
counter<=0;
else if (run)
if (counter==delay)
counter<=0;
else counter<=counter+1;
//tmp
always@(posedge clk or negedge rst_int)
if(!rst_int)
tmp<=0;
else if (tmp==4'h6)
tmp<=0;
else if(counter==delay)
tmp<=tmp+1;
//state machine
always@(posedge clk or negedge rst_int)
if(!rst_int)
state<=`IDLE;
else
case (state)
`IDLE: if(run) state<=`S1;
`S1: if(ledreg==8'h00&&counter==delay) state<=`S2;
`S2: if(ledreg==8'h00&&counter==delay) state<=`S3;
`S3: if(ledreg==8'h00&&counter==delay) state<=`S4;
`S4: if(ledreg==8'h00&&counter==delay) state<=`IDLE;
default: state<=`IDLE;
endcase
//LED reg
always@(posedge clk or negedge rst_int)
if(!rst_int)
ledreg<=0;
else if(state==`IDLE)
ledreg<=0;
else if(state==`S1) // pattern 1
begin
if (tmp==0)
ledreg<=8'b10001000;
else if (counter==delay)
begin
ledreg[7]<=1'b0;
ledreg[6]<=ledreg[7];
ledreg[5]<=ledreg[6];
ledreg[4]<=ledreg[5];
ledreg[3]<=1'b0;
ledreg[2]<=ledreg[3];
ledreg[1]<=ledreg[2];
ledreg[0]<=ledreg[1];
end
end
else if (state==`S2) // pattern 2
begin
if (tmp==0)
ledreg<=8'b00010001;
else if (counter==delay)
begin
ledreg[4]<=1'b0;
ledreg[5]<=ledreg[4];
ledreg[6]<=ledreg[5];
ledreg[7]<=ledreg[6];
ledreg[0]<=1'b0;
ledreg[1]<=ledreg[0];
ledreg[2]<=ledreg[1];
ledreg[3]<=ledreg[2];
end
end
else if (state==`S3) // pattern 3
begin
if (tmp==0)
ledreg<=8'b00011000;
else if (counter==delay)
begin
ledreg[4]<=1'b0;
ledreg[5]<=ledreg[4];
ledreg[6]<=ledreg[5];
ledreg[7]<=ledreg[6];
ledreg[3]<=1'b0;
ledreg[2]<=ledreg[3];
ledreg[1]<=ledreg[2];
ledreg[0]<=ledreg[1];
end
end
else if (state==`S4) // pattern 4
begin
if (tmp==0)
ledreg<=8'b10000001;
else if (counter==delay)
begin
ledreg[7]<=1'b0;
ledreg[6]<=ledreg[7];
ledreg[5]<=ledreg[6];
ledreg[4]<=ledreg[5];
ledreg[0]<=1'b0;
ledreg[1]<=ledreg[0];
ledreg[2]<=ledreg[1];
ledreg[3]<=ledreg[2];
end
end
// outpur LED
assign LED=ledreg;
endmodule
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